Germany plans to invest 45M euro with the aim of developing “trustworthy” electronics and improving competences in processor development.

For comparison, Intel R&D expenses are 13B$ every year.

The fantastic book is finally generally available now!

Efficient Processing of Deep Neural Networks
This tutorial covers all aspects of model software and hardware design related to the this topic. Explain very key concepts of weight/output/input/row stationarities and dataflow, power budget tradeoffs and hardware-software co-design aspects.

#Mipsology #Zebra https://www.allaboutcircuits.com/news/ai-accelerating-software-gives-fpgas-leg-up-gpu/

Sorry guys, this channel is transforming into link-collection feed, but I promise to be back on track soon with brief summaries :)

https://www.electronicdesign.com/industrial-automation/article/21136402/smartnic-architectures-a-shift-to-accelerators-and-why-fpgas-are-poised-to-dominate

Bluspec Haskell is an open-source framework, yet another High Level Hardware Description Language, but now based on Haskell

Jonathan Ross, hardware AI startup Groq founder and ex-Google TPU developer, claims that it was used on initial stages of TPU design. It looks like Groq is also actively using it
https://www.linkedin.com/in/jonathan-ross-12a95156/

Bluespec research note
https://arxiv.org/pdf/1905.03746.pdf

The latest version of bluespec Compiler can be found here
https://github.com/B-Lang-org/bsc

And here's the tutorial
https://github.com/rsnikhil/Bluespec_BSV_Tutorial/tree/master/Reference

Syntiant, a startup developing AI edge hardware for voice and sensor solutions, today closed a $35 million round. CEO Kurt Busch says the funds will be used to ramp up production throughout the remainder of 2020.

The one million parts shipped to date includes both NDP100 and NDP101 parts since the company’s first production orders in September 2019. Both are manufactured at UMC in Singapore

Syntiant’s NPD100 and NPD101 processors measure about 1.4 millimeters by 1.8 millimeters and can run models with over half a million parameters. Packing a general-purpose ARM Cortex-M0 processor paired with 128KB of RAM, the chips consume less than 140 microwatts and enable onboard firmware security and authentication, keyword training, and up to 64 output classifications.

The NPD100 and NPD101 — which initially targeted performance of around 20 TOPS (trillion floating-point operations) per watt — use hundreds of thousands of flash memory NOR cells that read and write data one word or byte at a time. The processor-in-memory architecture was proposed by CTO Jeremy Holleman, a researcher at the University of North Carolina in Charlotte, as far back as the 2014 International Solid-State Circuits Conference. Syntiant asserts that the architecture is ideal for executing massively parallel operations in deep learning at low power.

According to a report published by Meticulous Research, the speech and voice recognition hardware market is expected to reach $26.8 billion by 2025

Article on the EET
Syntiant Webpage

NDP100 Overview

#nonhw

https://api.deepai.org/publication-download-pdf/can-your-ai-differentiate-cats-from-covid-19-sample-efficient-uncertainty-estimation-for-deep-learning-safety

SoA Deep Neural Networks and Bayesian Neural Networks failed to distinguish cat and chest X-Ray image.

A DomainSpecific Supercomputer for Training Deep Neural Networks

Google supercomputer, 4096 TPU v3 chips in a 2D torus topology, wins MLPerf benchmark contest, the result table was published published on 29th of July.
Note also that it's probably the first TPU v4 public release. It currently shows with a pretty moderate result - 3.5 times slower than a winner.
But it has 8 times less chips (256) , so it looks like Google will beat it's own record very soon, whenever they upscale TPUv4 supercomputer up to 1024 chips.

❓ Can I run my Neural Network on the FPGA?
❓ Does Vivado HLS run my CPP code on the FPGA?
❓ What is difference between OneAPI and Intel OpenCL?
❓ Vitis - is it a sort of HLS for VIvado, isn't it?
🤔

There are two main FPGA vendors today - Xilinx and Intel. Both of them released dozens of different software developer oriented tools during the last couple of year. All of them promises the same - run you software on FPGA in a few clicks.

😕 It's a bit tricky to get through all these marketing papers and understand the role of each new thing.

📖 Here's the paper which should navigate you through all these applications and IDEs.

📝 Feel free to comment it right in the Google docs